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description the a1190, A1192, and a1193 comprise a family of two- wire, unipolar, hall-effect switches, which can be trimmed by the user at end-of-line to optimize magnetic switchpoint accuracy in the application. these devices are produced on the allegro ? advanced bicmos wafer fabrication process, which implements a patented high frequency, 4-phase, chopper-stabilization technique. this technique achieves magnetic stability over the full operating temperature range, and eliminates offsets inherent in devices with a single hall element that are exposed to harsh application environments. the a119x family has a number of automotive applications. these include sensing seat track position, seat belt buckle presence, hood/trunk latching, and shift selector position. two-wire unipolar switches are particularly advantageous in cost-sensitive applications because they require one less wire for operation versus the more traditional open-collector output switches. additionally, the system designer inherently gains diagnostics because there is always output current flowing, which should be in either of two narrow ranges. any current level not within these ranges indicates a fault condition. all family members are offered in two package styles. the lh is a sot-23w style, miniature, low profile package for surface- mount applications. the ua is a 3-pin, ultra-mini, single inline package (sip) for through-hole mounting. both packages are lead (pb) free, with 100% matte tin leadframe plating. a1190-ds, rev. 3 features and benefits ? high speed, 4-phase chopper stabilization ? low switchpoint drift throughout temperature range ? low sensitivity to thermal and mechanical stresses ? on-chip protection ? supply transient protection ? reverse battery protection ? on-board voltage regulator ? 3.0 to 24 v operation ? solid-state reliability ? robust emc and esd performance ? field programmable for optimized switchpoints ? industry leading iso 7637-2 performance through use of proprietary, 40-v clamping structure programmable, chopper-stabilized, two wire hall-effect switches functional block diagram a1190, A1192 and a1193 amp regula to all subcircuits tor schmitt trigger polarity low-pass filter gnd vcc program / lock i cc adjust offset adjust gnd ua package only 0.01 f v+ clock/logic dynamic offset cancellation sample and hold packages approximate footprint 3-pin sot23-w 2 mm 3 mm 1 mm (suffix lh) 3-pin ultramini sip 1.5 mm 4 mm 3 mm (suffix ua)
programmable, chopper-stabilized, two wire hall-effect switches a1190, A1192, and a1193 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com nc 1 2 3 1 3 2 pin-out diagrams lh package ua package absolute maximum ratings characteristic symbol notes rating unit forward supply voltage v cc 28 v reverse supply voltage v rcc ?18 v magnetic flux density b unlimited g operating ambient temperature t a range l ?40 to 150 oc maximum junction temperature t j (max) 165 oc storage temperature t stg ?65 to 170 oc selection guide part number package packing 1 output (i cc ) in south polarity field supply current at i cc(l) (ma) magnetic operate point, b op (g) a1190llhlt-t 2 lh (surface mount) 7-in. reel, 3000 pieces/reel low 2 to 5 10 to 200 a1190llhlx-t lh (surface mount) 13-in. reel, 10 000 pieces/reel a1190lua-t 3 ua (through hole) bulk, 500 pieces/bag A1192llhlt-t 2 lh (surface mount) 7-in. reel, 3000 pieces/reel low 5 to 6.9 A1192llhlx-t lh (surface mount) 13-in. reel, 10 000 pieces/reel A1192lua-t 3 ua (through hole) bulk, 500 pieces/bag a1193llhlt-t 2 lh (surface mount) 7-in. reel, 3000 pieces/reel high a1193llhlx-t lh (surface mount) 13-in. reel, 10 000 pieces/reel a1193lua-t 3 ua (through hole) bulk, 500 pieces/bag 1 contact allegro ? for additional packing options. 2 these variants available only through authorized distributors. 3 contact factory for availability. terminal list table number name function lh package ua package 1 vcc vcc connects power supply to chip; used to apply programming signal 2 nc gnd lh package: no connection ua package: ground terminal 3 gnd gnd ground terminal
electrical characteristics valid at t a = ?40c to 150c, t j < t j (max), c byp = 0.01 f, through operating supply voltage range; unless otherwise noted characteristics symbol test conditions min. typ. max. unit supply voltage 1,2 v cc operating, t j 165 c 3.0 ? 24 v supply current i cc(l) a1190 b > b op 2.0 ? 5.0 ma A1192 b > b op 5 ? 6.9 ma a1193 b < b rp 5 ? 6.9 ma i cc(h) a1190, A1192 b < b rp 12 ? 17 ma a1193 b > b op 12 ? 17 ma supply zener clamp voltage v z(sup) i cc = i cc(l) (max) + 3 ma, t a = 25c 28 ? ? v supply zener clamp current i z(sup) v z(sup) = 28 v ? ? i cc(l) (max) + 3 ma ma reverse supply current i rcc v rcc = ?18 v ? ? ?1.6 ma output slew rate 3 di/dt no bypass capacitor, capacitance of probe c s = 20 pf ?90?ma / s chopping frequency f c ? 700 ? khz power-up time 2,4,5 t on a1190, A1192 c byp = 0.01 f, b > b op + 10 g ? ? 25 s a1193 c byp = 0.01 f, b < b rp ? 10 g ? ? 25 s power-up state 6,7 pos t on < t on (max) , v cc slew rate > 25 mv / s?i cc(h) ?? 1 v cc represents the generated voltage between the vcc pin and the gnd pin. 2 the v cc slew rate must exceed 600 mv/ms from 0 to 3 v. a slower slew rate through this range can affect device performance. 3 measured without bypass capacitor between vcc pin and the gnd pin. use of a bypass capacitor results in slower current change. 4 power-up time is measured without and with a bypass capacitor of 0.01 f. adding a larger bypass capacitor would cause longer power-up time. 5 guaranteed by characterization and design. 6 power-up state as defined is true only with a v cc slew rate of 25 mv / s or greater. 7 for t > t on and b rp < b < b op , power-up state is not defined. magnetic characteristics 1 valid at t a = ?40c to 150c, t j t j (max); unless otherwise noted characteristics symbol test conditions min. typ. max. unit 2 initial operate point b op(init) ? ?14 10 g programmable magnetic operating point b op t a = 25c 10 ? 200 g average magnetic step size 3 step bop t a = 25c, v cc = 5 v 3 4.8 7.5 g switchpoint temperature drift b op ? 20 ? g hysteresis b hys 5 ? 30 g 1 relative values of b use the algebraic convention, where positive values indicate south magnetic polarity, and negative values indicate north magnetic polarity; therefore greater b values indicate a stronger south polarity field (or a weaker north polarity field, if pr esent). 2 1 g (gauss) = 0.1 mt (millitesla). 3 step bop is a calculated average from the cumulative programmed bits. programmable parameters name functional description quantity of bits b op trim fine trim of programmable magnetic operating point 6 programming lock lock access to programming 1 programmable, chopper-stabilized, two wire hall-effect switches a1190, A1192, and a1193 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
6 7 8 9 2 3 4 5 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 20 40 60 80 100 120 140 160 180 temperature (oc) maximum allowable v cc (v) power derating curve (r q ja = 228 oc/w) 4-layer pcb, package lh (r q ja = 110 oc/w) 2-layer pcb, package lh (r q ja = 165 oc/w) 1-layer pcb, package ua v cc(min) v cc(max) 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 20 40 60 80 100 120 140 160 180 temperature (c) power dissipation, p d (m w) power dissipation versus ambient temperature (r q ja = 165 oc/w) 1-layer pcb, package ua (r q ja = 228 oc/w) 4-layer pcb, package lh (r q ja = 110 oc/w) 2-layer pcb, package lh thermal characteristics may require derating at maximum conditions, see application information characteristic symbol test conditions* value unit package thermal resistance r ja package lh, on 4-layer pcb based on jedec standard 228 oc/w package lh, on 2-layer pcb with 0.463 in. 2 of copper area each side 110 oc/w package ua, on 1-layer pcb with copper limited to solder pads 165 oc/w *additional thermal information available on the allegro website programmable, chopper-stabilized, two wire hall-effect switches a1190, A1192, and a1193 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
characteristic performance v cc = 3.0 v v cc = 24 v -60 -40 -20 0 20 40 60 80 100 140 120 160 ambient temperature, t a (c) supply current, i cc(h) (ma) 17 16 15 14 13 12 average supply current (high) versus temperature a1190/A1192/a1193 v cc = 3.0 v v cc = 24 v 7.0 6.5 6.0 5.5 5.0 -60 -40 -20 0 20 40 60 80 100 140 120 160 ambient temperature, t a (c) supply current, i cc(l) (ma) v cc = 3.0 v v cc = 24 v 5.0 4.5 4.0 3.5 3.0 2.5 2.0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 -60 -40 -20 0 20 40 60 80 100 140 120 160 ambient temperature, t a (c) supply current, i cc(l) (ma) average supply current (low) versus temperature A1192 and a1193 average supply current (low) versus temperature a1190 supply voltage, v cc (v) supply current, i cc(h) (ma) 17 16 15 14 13 12 2 6 10 14 18 22 26 t a = 150c t a = ?40c t a = 25c average supply current (high) versus supply voltage a1190/A1192/a1193 t a = 150c t a = ?40c t a = 25c 7.0 6.5 6.0 5.5 5.0 2 6 10 14 18 22 26 supply voltage, v cc (v) supply current, i cc(l) (ma) t a = 150c t a = ?40c t a = 25c 2 6 10 14 18 22 26 supply voltage, v cc (v) supply current, i cc(l) (ma) average supply current (low) versus supply voltage A1192 and a1193 average supply current (low) versus supply voltage a1190 programmable, chopper-stabilized, two wire hall-effect switches a1190, A1192, and a1193 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
v cc = 3.0 v v cc = 24 v ambient temperature, t a (c) -60 -40 -20 0 20 40 60 80 100 140 120 160 30 25 20 15 10 5 applied flux density at switchpoint hysteresis, b hys (g) ambient temperature, t a (c) -60 -40 -20 0 20 40 60 80 100 140 120 160 bit #5 bit #4 bit #3 bit #2 bit #1 bit #0 160 140 120 100 80 60 40 20 0 -20 average operate point, b op (g) code 0 4 8 12 16 20 24 28 32 36 b op(init) average switchpoint hysteresis versus temperature average operate point versus code a1190/A1192/a1193 a1190/A1192/a1193 programmable, chopper-stabilized, two wire hall-effect switches a1190, A1192, and a1193 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
functional description b op b rp b hys i cc(h) i cc i cc(l) switch to low switch to high b+ b? i+ 0 (a) hysteresis curve for a1190 and A1192 b op b rp b hys i cc(h) i cc i cc(l) switch to high switch to low b+ i+ b? 0 (b) hysteresis curve for a1193 figure 1. alternative switching behaviors are available in the a119x device family. on the horizontal axis, the b+ direction in dicates increasing south polarity magnetic field strength, and the b? direction indicates decreasing south polarity field strength (inc luding the case of increasing north polarity). the a1190 and A1192 output, i cc , switches low after the mag- netic field at the hall sensor ic exceeds the operate point thresh- old, b op . when the magnetic field is reduced to below the release point threshold, b rp , the device output goes high. this is shown in figure 1, panel a. in the case of the reverse output polarity, as in the a1193, the device output switches high after the magnetic field at the hall sensor ic exceeds the operate point threshold, b op . when the magnetic field is reduced to below the release point threshold, b rp , the device output goes low (panel b). the difference between the magnetic operate and release points is called the hysteresis of the device, b hys . this built-in hyster- esis allows clean switching of the output even in the presence of external mechanical vibration and electrical noise. programmable, chopper-stabilized, two wire hall-effect switches a1190, A1192, and a1193 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
figure 2. typical application circuits gnd a119x vcc v+ 0.01 f a gnd ecu package ua only a r sense c byp gnd a119x vcc v+ 0.01 f a gnd r sense c byp (a) low side sensing (b) high side sensing figure 3. chopper stabilization circuit (dynamic quadrature offset cancellation) amp regulator clock/logic hall element sample and hold low-pass filter chopper stabilization technique when using hall-effect technology, a limiting factor for switchpoint accuracy is the small signal voltage developed across the hall element. this voltage is disproportionally small relative to the offset that can be produced at the output of the hall sensor ic. this makes it difficult to process the signal while maintaining an accurate, reliable output over the specified oper- ating temperature and voltage ranges. chopper stabilization is a unique approach used to minimize hall offset on the chip. the patented allegro technique, namely dynamic quadrature offset cancellation, removes key sources of the output drift induced by thermal and mechanical stresses. this offset reduction technique is based on a signal modulation-demodulation process. the undesired offset signal is separated from the magnetic field- induced signal in the frequency domain, through modulation. the subsequent demodulation acts as a modulation process for the offset, causing the magnetic field-induced signal to recover its original spectrum at base band, while the dc offset becomes a high-frequency signal. the magnetic-sourced signal then can pass through a low-pass filter, while the modulated dc offset is suppressed. the chopper stabilization technique uses a 350 khz high frequency clock. for demodulation process, a sample and hold technique is used, where the sampling is performed at twice the chopper frequency. this high-frequency operation allows a greater sampling rate, which results in higher accuracy and faster signal-processing capability. this approach desensitizes the chip to the effects of thermal and mechanical stresses, and produces devices that have extremely stable quiescent hall out- put voltages and precise recoverability after temperature cycling. this technique is made possible through the use of a bicmos process, which allows the use of low-offset, low-noise amplifiers in combination with high-density logic integration and sample- and-hold circuits. programmable, chopper-stabilized, two wire hall-effect switches a1190, A1192, and a1193 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
programming guidelines overview programming is accomplished by sending a series of input volt- age pulses serially through the vcc (supply) pin of the device. a unique combination of different voltage level pulses controls the internal programming logic of the device to select a desired programmable parameter and change its value. there are three voltage levels that must be taken into account when program- ming. these levels are referred to as high (v ph ), mid (v pm ), and low (v pl ) (see figure 1 and table 1). the a119x family features two programmable modes, try mode and blow mode. ? in try mode, programmable parameter values are set and mea- sured. a parameter value is stored temporarily, and reset after cycling the supply voltage. ? in blow mode, the value of a programmable parameter may be permanently set by blowing solid-state fuses internal to the device. device locking is also accomplished in this mode. the programming sequence is designed to help prevent the device from being programmed accidentally; for example, as a result of noise on the supply line. although any programmable variable power supply can be used to generate the pulse wave- forms, allegro highly recommends using the allegro sensor ic evaluation kit, available on the allegro website on-line store. the manual for that kit is available for download free of charge, and provides additional information on programming these devices. definition of terms register . the section of the programming logic that controls the choice of programmable modes and parameters. bit field . the internal fuses unique to each register, represented as a binary number. changing the bit field selection in a particu- lar register causes its programmable parameter to change, based on the internal programming logic. key . a series of v pm voltage pulses used to select a register or mode. table 1. programming pulse requirements , protocol at t a = 25c (refer also to figure 4) characteristic symbol notes min. typ. max. unit programming voltage v pl measured at the vcc pin. 4.5 5 5.5 v v p m 12.5 ? 14 v v ph 21 ? 27 v programming current i pp t pr = 11 s, v cc = 5 26 v, c blow = 0.1 f (min). minimum supply current required to ensure proper fuse blowing. c blow must be connected between the vcc and gnd pins during programming to provide the current necessary for fuse blowing. 175 ? ? ma pulse width t low duration at v pl separating pulses at v pm or v ph .20?? s t active duration of pulses at v pm or v ph for key/code selection. 20 ? ? s t blow duration of pulse at v ph for fuse blowing. 90 100 ? s pulse rise time t pr v pl to v pm , or v pl to v ph . 5 ? 100 s pulse fall time t pf v ph to v pl , or v pm to v pl . 5 ? 100 s blow pulse slew rate sr blow 375 ? ? mv/ s supply voltage, v cc 0 (supply cycled) programming pulses blow pulse t active t low t low t blow t pr t pf v ph v pm v pl figure 4. programming pulse definition (see table 1) programmable, chopper-stabilized, two wire hall-effect switches a1190, A1192, and a1193 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
programmable, chopper-stabilized, two wire hall-effect switches a1190, A1192, and a1193 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com table 2. programming logic table register bit field address (code) description key name binary format [msb lsb] decimal equivalent try mode 0b op trim up counting 000000 0 initial value (below minimum |b op | ) (try mode sequence starts with code 1); code corresponds to bit field value (code 1 selects bit field value 000001) 111111 63 maximum selectable value (above maximum |b op | ) 1b op trim down counting 111111 0 initial value (above maximum |b op | ) (try mode sequence starts with code 1); code is automatically inverted (code 1 selects bit field value 111110) 000000 63 minimum selectable value (below minimum |b op |) 7 fuse check 000111 7 check integrity of all fuse bits versus low threshold 0 0 11 1 1 15 check integrity of all fuse bits versus high threshold blow mode 0b op trim 000000 0 initial value (below minimum |b op | ); (only allows selection of 1 bit per sequence) 111111 63 maximum selectable value (above maximum |b op | ); (only allows selection of 1 bit per sequence) 7 programming lock 001000 8 locks out access to all registers except fuse check code . the number used to identify the combination of fuses activated in a bit field, expressed as the decimal equivalent of the binary value. the lsb of a bit field is denoted as code 1, or bit 0. addressing . setting the bit field code in a selected register by serially applying a pulse train through the vcc pin of the device. each parameter can be measured during the addressing process, but the internal fuses must be blown before the programming code (and parameter value) becomes permanent. fuse blowing . applying a v ph pulse of sufficient duration to permanently set an addressed bit by blowing a fuse internal to the device. once a bit (fuse) has been blown, it cannot be reset. blow pulse . a v ph pulse of sufficient duration to blow the addressed fuse. cycling the supply . powering-down, and then powering-up the supply voltage. cycling the supply is used to clear the program- ming settings in try mode. programming procedure programming involves selection of a register, a mode, and then setting values for parameters in the register for evaluation or for fuse blowing. figure 10 provides an overview state diagram. register selection each programmable parameter can be accessed through a specific register. to select a register, a sequence of voltage pulses consisting of a v ph pulse, a series of v pm pulses, and a v ph pulse (with no v cc supply interruptions) must be applied serially to the vcc pin. the quantity of v pm pulses is called the key , and uniquely identifies each register. the pulses for selection of register key 1, is shown in figure 5. no v pm pulse is sent for key 0. the register selections are shown in table 2. mode selection after register selection, the mode is selected, either try or blow mode. try mode is selected by default. to select blow mode, that mode selection key must be sent.
programmable, chopper-stabilized, two wire hall-effect switches a1190, A1192, and a1193 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com try mode in try mode, bit field addressing is accomplished by applying a series of v pm pulses to the vcc pin of the device, as shown in figure 6. each pulse increases the bit field value for the selected parameter, increasing by one on the falling edge of each additional v pm pulse. when addressing the bit field in try mode, the quantity of v pm pulses is represented by a decimal number called the code . addressing activates the corresponding fuse locations in the given bit field by increasing the binary value of an internal dac, up to the maximum possible code. as the value of the bit field code increases, the value of the programmable parameter changes. measurements can be taken after each v pm pulse to determine if the required result for the programmable parameter has been reached. cycling the supply voltage resets all the locations in the bit field that have un-blown fuses to their initial states. when setting the b op trim parameter, as an aid to programming, values can be traversed from low to high, or from high to low. to accommodate this direction selection, the value of the bit field (and code) defaults to the value 1, on the falling edge of the final register selection v ph pulse (see figure 5). a complete example is provided in figure 11. blow mode after the required code is determined for a given parameter, its value can be set permanently by blowing individual fuses in the appropriate register bit field. blowing is accom- plished by selecting the register, then the blow mode selection key, followed by the appropriate bit field address, and ending the sequence with the blow pulse. the blow mode selection key is a sequence of nine v pm pulses followed by one v ph pulse. a complete example is provided in figure 12. the blow pulse consists of a v ph pulse of sufficient duration, t blow , to permanently set an addressed bit by blowing a fuse internal to the device. due to power requirements, the fuse for each bit in the bit field must be blown individually. the a119x family built-in circuitry allows only one fuse at a time to be blown. during blow mode, the bit field can be considered a ?one- hot? shift register. table 3 relates the quantity of v pm pulses to the binary and decimal values for blow mode bit field address- ing. it should be noted that the simple relationship between the quantity of v pm pulses and the corresponding code is: 2 n = code, where n is the quantity of v pm pulses. the bit field has an initial state of decimal code 0 (binary 000000). figure 6. try mode bit field addressing pulses figure 7. example of code 5 broken into its binary components supply voltage, v cc 0 v ph v pm v pl code 2 code 3 code 2 n ? 2 code 2 n ? 1 table 3. blow mode bit field addressing quantity of v pm pulses binary register setting equivalent code 1 000001 1 2 000010 2 3 000100 4 4 001000 8 5 010000 16 6 100000 32 (decimal equivalent) code 5 bit field selection address code format code in binary fuse blowing target bits fuse blowing address code format (binary) 1 0 1 bit 2 bit 0 code 4 code 1 (decimal equivalents) supply voltage, v cc 0 key v ph v pm v pl figure 5. register selection pulse sequence
programmable, chopper-stabilized, two wire hall-effect switches a1190, A1192, and a1193 12 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com to correctly address the fuses to be blown, the code represent- ing the required parameter value must be translated into a binary number. for example, as shown in figure 7, decimal code 5 is equivalent to the binary number 101. therefore bit 2 must be addressed and blown, the device power supply cycled, and then bit 0 must be addressed and blown. the order of blowing bits, however, is not important. blowing bit 0 first, and then bit 2 is acceptable. note: after blowing, the programming is not reversible, even after cycling the supply power. although a register bit field fuse cannot be reset after it is blown, additional bits within the same register can be blown at any time until the device is locked. for example, if bit 1 (binary 10) has been blown, it is still possible to blow bit 0. the end result would be binary 11 (decimal code 3). locking the device after the required code for each parameter is programmed, the device can be locked to prevent further programming of any parameters. to do so, perform the following steps: 1. ensure that the c blow capacitor is mounted. 2. select the programming lock register (key 7). 3. select blow mode (key 9). 4. address bit 3 (001000) by sending four v pm pulses. 5. send one blow pulse, at i pp and sr blow , and sustain it for t blow . 6. delay for a t low interval, then power-down. 7. optionally check all fuses. fuse checking incorporated in the a119x family is circuitry to simultaneously check the integrity of the fuse bits. the fuse checking feature is enabled by using the fuse check register (selection key 7), and while in try mode, applying the codes shown in table 2. the register is only valid in try mode and is available before or after the programming lock bit is set. setting the fuse threshold high checks that all blown fuses are properly blown. setting fuse threshold low checks all un-blown fuses are properly intact. the supply current increases by 250 a if a marginal fuse is detected. if all fuses are correctly blown or fully intact, there will be no change in supply current. additional guidelines the additional guidelines in this section should be followed to ensure the proper behavior of these devices: ? a 0.1 f blowing capacitor, c blow , must be mounted between the vcc pin and the gnd pin during programming, to ensure enough current is available to blow fuses. ? the power supply used for programming must be capable of delivering at least v ph and 175 ma. ? be careful to observe the t low delay time before powering down the device after blowing each bit. ? lock the device (only after all other parameters have been pro- grammed and validated) to prevent any further programming of the device. b op selection selecting b op should be done in two stages. first, try mode should be used to adjust b op and monitor the output state. then the optimum b op is set permanently using blow mode. use the b op trim up counting register to increase the b op selec- tion by one magnetic step size, step bop , increment with each bit field pulse (see figure 8). use the b op trim down counting register to decrease the b op selection by one step bop with each bit field pulse (see figure 9). as an aid to programming, when using down-counting method, the a119x automatically inverts the bit field selection (code 0 in down-counting sets the bit field value 111111, and the actual bit field value decreases until code 63 sets bit field value 000000). note that the release point, b rp , is a value below b op . the difference is specified by the hysteresis, b hys , which is not programmable.
programmable, chopper-stabilized, two wire hall-effect switches a1190, A1192, and a1193 13 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 8. b op selection up counting figure 9. b op selection down counting |b op (max)| |b op (min)| |b op (max)| |b op (min)| try mode, bit field code 03163 b op b rp b hys (code 0, bit value 111111 ) b op b rp b hys (code 63, bit value 000000) try mode, bit field code 03163 b op b rp b hys (code 0, bit value 000000 ) b op b rp b hys (code 63, bit value 111111 )
programmable, chopper-stabilized, two wire hall-effect switches a1190, A1192, and a1193 14 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 10. programming state diagram figure 11. example of try mode pulse sequence, register key = b op selection down counting figure 12. example of blow mode pulse sequence, register key = b op selection bit field 2 (code 4)
power derating programmable, chopper-stabilized, two wire hall-effect switches a1190, A1192, and a1193 15 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the device must be operated below the maximum junction tem- perature of the device, t j (max). under certain combinations of peak conditions, reliable operation may require derating supplied power or improving the heat dissipation properties of the appli- cation. this section presents a procedure for correlating factors affecting operating t j . (thermal data is also available on the allegro microsystems web site.) the package thermal resistance, r ? ja , is a figure of merit sum- marizing the ability of the application and the device to dissipate heat from the junction (die), through all paths to the ambient air. its primary component is the effective thermal conductivity, k, of the printed circuit board, including adjacent devices and traces. radiation from the die through the device case, r ? jc , is relatively small component of r ? ja . ambient air temperature, t a , and air motion are significant external factors, damped by overmolding. the effect of varying power levels (power dissipation, p d ), can be estimated. the following formulas represent the fundamental relationships used to estimate t j , at p d . p d = v in i in (1) ? ???????????????????????? t = p d r ? ja (2) t j = t a + t (3) for example, given common conditions such as: t a = 25c, v cc = 12 v, i cc = 4 ma, and r ? ja = 140 c/w, then: p d = v cc i cc = 12 v 4 ma = 48 mw ?? t = p d r ? ja = 48 mw 140 c/w = 7c t j = t a + ? t = 25c + 7c = 32c a worst-case estimate, p d (max), represents the maximum allow- able power level (v cc (max), i cc (max)), without exceeding t j (max), at a selected r ? ja and t a . example : reliability for v cc at t a = 150c, package ua, using a low-k pcb. observe the worst-case ratings for the device, specifically: r ? ja = 165 c/w, t j (max) = 165c, v cc (max) = 24 v, and i cc (max) = 17 ma. calculate the maximum allowable power level, p d (max). first, invert equation 3: ? t max = t j (max) ? t a = 165 c ? 150 c = 15 c this provides the allowable increase to t j resulting from internal power dissipation. then, invert equation 2: ???? p d (max) = ? t max r ? ja = 15c 165 c/w = 91 mw finally, invert equation 1 with respect to voltage: v cc(est) = p d (max) i cc (max) = 91 mw 17 ma = 5 v the result indicates that, at t a , the application and device can dissipate adequate amounts of heat at voltages v cc(est) . compare v cc(est) to v cc (max). if v cc(est) v cc (max), then reli- able operation between v cc(est) and v cc (max) requires enhanced r ? ja . if v cc(est) v cc (max), then operation between v cc(est) and v cc (max) is reliable under these conditions.
programmable, chopper-stabilized, two wire hall-effect switches a1190, A1192, and a1193 16 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package lh, 3-pin sot23w 0.55 ref gauge plane seating plane 0.25 bsc 0.95 bsc 0.95 1.00 0.70 2.40 2 1 a active area depth, 0.28 mm ref b c c b reference land pattern layout all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances branding scale and appearance at supplier discretion a pcb layout reference view standard branding reference view 1 branded face n = last two digits of device part number t = temperature code nnt 2.90 +0.10 ?0.20 44 8x 10 ref 0.180 +0.020 ?0.053 0.05 +0.10 ?0.05 0.25 min 1.91 +0.19 ?0.06 2.98 +0.12 ?0.08 1.00 0.13 0.40 0.10 for reference only; not for tooling use (reference dwg-2840) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown d hall element, not to scale d d d 1.49 0.96 3
programmable, chopper-stabilized, two wire hall-effect switches a1190, A1192, and a1193 17 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package ua, 3-pin sip 23 1 1.27 nom 1.02 max 45 45 c 1.52 0.05 b gate and tie bar burr area a b c dambar removal protrusion (6x) a d e d e e 1.44 nom 2.05 nom e active area depth, 0.50 mm ref branding scale and appearance at supplier discretion hall element (not to scale) for reference only; not for tooling use (reference dwg-9065) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown standard branding reference view nnn 1 mold ejector pin indent = supplier emblem n = last three digits of device part number 0.41 +0.03 ?0.06 0.43 +0.05 ?0.07 14.99 0.25 4.09 +0.08 ?0.05 3.02 +0.08 ?0.05 0.79 ref 10 branded face
programmable, chopper-stabilized, two wire hall-effect switches a1190, A1192, and a1193 18 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com for the latest version of this document, visit our website: www.allegromicro.com copyright ?2009-2011, allegro microsystems, inc. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. revision history revision revision date description of revision rev. 3 november 17, 2011 update product selection and v cc , t on , t blow , and programming lock

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